The present invention relates to a technology for testing a semiconductor integrated circuit equipped with a memory cell array and, more particularly, to a technology which is effective if applied to a semiconductor memory device equipped with a test circuit.
A tester to be used for testing a semiconductor memory device decides the propriety of the semiconductor memory device by sequentially generating a testing data pattern and an address signal, by causing the semiconductor memory device to perform the write/read operations cyclically, and by comparing the read data consecutively with a prospective data by a comparator. However, the number of comparators owned by the tester is limited, and the number of semiconductor memory devices to be tested at one time is necessarily reduced by the number of the parallel output bits of the semiconductor memory device to be tested. Thus, it grows difficult to test a number of semiconductor memory devices efficiently all at once.
Japanese Patent Laid-Open No. 282799/1989 has disclosed the on-chip technique of a test circuit, in which the comparison between the read data from the memory cell array and a protective value and the latch of the comparison result are accomplished in the semiconductor memory device. In addition, a semiconductor memory device having the test circuit packaged therein is disclosed in Japanese Patent Laid-Open No. 62899/1989 or 16929/1981.